1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and method for driving the same.
2. Description of the Related Art
Conventionally, cathode-ray tubes (CRTs) have been used as display devices. Presently, much effort is being made to study and develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FEDs), and electro-luminescence displays (ELDs), as a substitute for CRTs. These flat panel displays may be driven by an active matrix driving method in which a plurality of pixels arranged in a matrix configuration are driven using a plurality of corresponding thin film transistors. Among these active matrix type flat panel displays, liquid crystal display (LCD) devices and electroluminescent display (ELD) devices are widely used for notebook computers and desktop monitors, among others, because of their high resolution, ability to display colors, and superiority in displaying moving images.
In general, an LCD device includes two substrates that are spaced apart and face each other with a layer of liquid crystal interposed between the two substrates. The two substrates typically include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the layer of liquid crystal. The alignment of the liquid crystal molecules changes based on the intensity of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the electric field across the layer of liquid crystal.
FIG. 1 is a block diagram illustrating an LCD device according to the related art. As shown in FIG. 1, the LCD device includes a liquid crystal panel 12, a driving circuit having gate and source drivers 8 and 10 and a timing controller 6, and an interface 4. The interface 4 is supplied with control signals and data signals from an exterior system 2, and transfers those signals to the timing controller 6. The timing controller 6 generates control signals to control the gate and source drivers 8 and 10. The timing controller 6 processes data signals and supplies the processed data signals to the source driver 10. The gate driver 8 is controlled by the control signals from the timing controller 6 and outputs gate voltage signals. The source driver 10 is controlled by the control signals from the timing controller 6 and outputs data voltage signals.
FIGS. 2A and 2B are waveform views illustrating control signals and gate and data voltage signals when a data enable signal has a normal state and an abnormal state, respectively, in the related art LCD device.
As illustrated in FIG. 2A, in a normal state operation, a data enable signal DE of a normal state having a normal width a1 is supplied. Accordingly, a gate output enable signal GOE, a gate shift clock GSC and a source output enable signal SOE of a normal state (i.e., having normal widths) are generated. Then, the gate driver 8 outputs gate voltage signals to respective gate lines GL1-GLn, and the source driver 10 outputs data voltage signals to respective data lines DL1-DLm based on the normal width a1 of the data enable signal DE. In other words, when the data enable signal DE has a normal width a1, the gate voltage signals have a normal width b1. Accordingly, the LCD device operates in a normal state.
However, when the power is initially turned on, or when various events such as a resolution change in the external system (2 of FIG. 1) occur, an abnormal data enable signal DE may be supplied. This may lead to an abnormal state operation. As illustrated in FIG. 2B, in the event that the width of the data enable signal DE abnormally decreases to a2, which is smaller than the normal width a1, then the widths of the gate output enable signal GOE and gate shift clock GSC pulses decrease correspondingly. As a result, the width of the gate voltage signals supplied to gate lines GL1 to GLn also decreases accordingly to b2, which is smaller than the normal width b1.
Accordingly, in the above abnormal state operation, the thin film transistors (TFTs) (not shown) in the LCD panel 12 are turned on for a shorter period of time than in the normal operation. As a result, the amount of time for charging pixel electrodes with corresponding data voltage signals through corresponding data lines DL1-DLm and thin film transistors (TFTs) is reduced. FIGS. 2A and 2B illustrate the data voltage signal supplied to one of the data lines (DL1) in the liquid crystal panel 12. The data voltage signal supplied to data line DL1 is inverted alternately with positive and negative polarities with each gate line.
Because the charging time is reduced, the pixel electrodes may not be charged sufficiently with corresponding data voltage signals. Thus, when the LCD device is operated with a normally white mode, for example, a flickering of white lines can occur. If this condition persists, it may lead to a degradation of display quality and deterioration of liquid crystal.